An analog-to-digital converter (ADC) is a common building block of modern integrated circuits. It is commonly used to sample an analog signal and convert it into digital values, which can, for example, be used for further digital processing. Different architectures are in use today to meet a wide range of requirements, such as linearity, conversion speed, noise, or power consumption. Examples of ADC architectures include flash ADC, linear approximation ADC, successive approximation ADC (SAR), sigma delta ADC, and others.
Successive approximation ADC is the name commonly given to an analog-to-digital conversion process in which digital approximations of the input analog voltage are determined on the basis of a binary search. A digital value stored in an n-bit successive approximation register (SAR) is input to a digital-to-analog converter, and a decision is made as to whether the value in the SAR represents an analog voltage that is higher or lower than the input analog value. The initial value of the SAR is conventionally set to one-half the number that can be represented in the n bits of the SAR. To be more precise, an n-bit register can contain a value of 2n−1, but for purposes of successive approximation, the initial value has the most significant bit set and the others cleared, which translates into a value of 2n/2. If this comparison reveals that the digital approximation is indeed lower than the input voltage, the bit that was initially set remains set, the bit of next lower significance is also set, and another trial commences. If on the other hand, the SAR value is greater than the input analog voltage, the bit that was set for that trial is cleared, the bit of next lower significance is set, and another trial commences. It can be appreciated from this example why a successive approximation approach bears such a similarity to a binary search procedure. Each bit of the SAR is set or cleared based upon a trial, so the analog to digital conversion process requires only “n” trials to reach completion. A conventional SAR converter consists of only a DAC (digital-to-analog converter), a SAR register, control logic, and a single comparator. To generate an n-bit conversion result, each component of the converter is used (or updated) n times in a series of what are known as bit trials.
One of the most common implementations of the successive approximation ADC, the charge-redistribution successive approximation ADC, uses a charge scaling DAC. The charge scaling DAC simply consists of an array of individually switched binary-weighted capacitors. The amount of charge upon each capacitor in the array is used to perform the aforementioned binary search in conjunction with a comparator internal to the DAC and the successive approximation register.
A disadvantage of traditional SAR ADC's is that a large number of clock cycles are necessary to implement a single n-bit conversion, resulting in a complicated state-machine running at a highly oversampled clock dissipating a lot of power.